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W78E62B 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78E62B is an 8-bit microcontroller which has an in-system programmable MTP-ROM for firmware updating. The instruction set of the W78E62B is fully compatible with the standard 8052. The W78E62B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which allows the contents of the 64KB main MTP-ROM to be updated by the loader program located at the 4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78E62B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E62B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
FEATURES
* * * * * * * * * * * * * * *
Fully static design 8-bit CMOS microcontroller up to 40 MHz. 64K bytes of in-system programmable MTP-ROM for Application Program (APROM). 4K bytes of auxiliary MTP-ROM for Loader Program (LDROM). Low standby current at full supply voltage. 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable) 64K bytes program memory address space and 64K bytes data memory address space. Four 8-bit bi-directional ports. One 4-bit multipurpose programmable port. Build-in 74373 and 74244 logical functions on Port 2.(software programmable) Three 16-bit timer/counters One full duplex serial port Eight-sources, two-level interrupt capability Built-in power management Code protection PACKAGE - PLCC 44: W78E62BP-40 - LQFP 48: W78E62BD-40
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Publication Release Date: June 1999 Revision A1
W78E62B
PIN CONFIGURATIONS
48-Pin LQFP (W78E62BD)
T 2 E X . P 1 . 1 / I N TT 23 .. PP 14 .. 02
N . C .
P 1 . 4
P 1 . 3
P 1 . 2
V D D
A D 0 . P 0 . 0
A D 1 . P 0 . 1
A D 2 . P 0 . 2
A D 3 . P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2,P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 N.C.
1 2 3 4 5
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
N.C. P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
6 7 8 9 10
27 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X T A L 1 VP S4 S. 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 N . C .
44-Pin PLCC (W78E62BP)
T 2 E X . P 1 . 1 3 / I N TT 23 .. PP 14 .. 02 2
P 1 . 4 6
P 1 . 3 5
P 1 . 2 4
V D D
A D 0 . P 0 . 0
A D 1 . P 0 . 1
A D 2 . P 0 . 2
A D 3 . P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2,P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
7 8
9 10 11 12 13 14 15
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X T A L 1 VP S4 S. 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
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W78E62B
PIN DESCRIPTION
SYMBOL EA TYPE I DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high and the program counter is within the 64 KB area. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE OH ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: Function is the same as that of standard 8052. PORT 1: Function is the same as that of standard 8052. PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. It also can be programmed to be an output-latched port like an on-chip 74373, or a buffer input port like an on-chip 74244. PORT 3: Function is the same as that of the standard 8052. PORT 4: A bi-directional I/O port with alternate function. See details below.
PSEN
OH
RST XTAL1 XTAL2 VSS VDD P0.0-P0.7 P1.0-P1.7 P2.0-P2.7
IL I O I I I/O D I/O H I/O H
P3.0-P3.7 P4.0-P4.3
I/O H I/O H
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Port 4 Port 4, SFR P4 at address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation mode: In mode 0, P4.0-P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt INT3 and INT2 if enabled. In mode 1, P4.0-P4.3 are read data strobe signals which are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals.
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W78E62B
In mode 2 , P4.0-P4.3 are write data strobe signals which are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. In mode 3, P4.0-P4.3 are read data strobe signals which are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode.
BLOCK DIAGRAM
P1.0
Port 1 Port 1 Latch ACC Interrupt T1 Timer 2 Timer 0 Timer 1 UART PSW ALU Stack Pointer T2
P1.7 B
Port 0 Latch Port 0
P0.0
P0.7
DPTR Temp Reg. PC
Incrementor
Addr. Reg.
P3.0
Port 3 Port 3 Latch Instruction Decoder & Sequencer SFR RAM Address 64KB MTP-ROM 4KB MTP-ROM
P3.7
512 bytes RAM & SFR
P2.0
Port 2 Latch Port 2
INT2 / INT3 Bus & Clock Controller
P2.7
P4.0 P4.3
Port 4
Port 4 Latch
Oscillator
Reset Block
Power control
XTAL1
XTAL2
ALE PSEN
RST
VCC
Vss
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W78E62B
FUNCTIONAL DESCRIPTION
The W78E62B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port, and an internal 74373 latch and 74244 buffer which can be switched to port2. The processor supports 111 different opcodes and references both a 64K program address space and a 64 K data storage space.
RAM
The internal data RAM in the W78E62B is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways. * RAM 0H-127H can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. * RAM 128H-255H can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank.
* AUX-RAM 0H-255H is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than 255H will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON.
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W78E62B
XICON - external interrupt control (C0H) PX3 PX3: EX3: IE3: IT3: PX2: EX2: IE2: IT2: EX3 IE3 IT3 PX2 EX2 IE2 IT2
External interrupt 3 priority high if set External interrupt 3 enable if set If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software External interrupt 2 priority high if set External interrupt 2 enable if set If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations: INTERRUPT SOURCE External Interrupt Timer/Counter 0 External Interrupt Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt External Interrupt 0 1 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH 33H 3BH POLLING SEQUENCE WITHIN PRIORITY LEVEL 0 (highest) 1 2 3 4 5 6 7 (lowest) ENABLE REQUIRED SETTINGS IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6 INTERRUPT TYPE EDGE/LEVEL TCON.0 TCON.2 XICON.0 XICON.3
2 3
Clock
The W78E62B is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E62B relatively insensitive to duty cycle variations in the clock.
Crystal Oscillator
The W78E62B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts.
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W78E62B
Power Management
Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT3 when enabled and set to level triggered.
Reduce EMI Emission
The W78E62B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1,C2 may need some adjustment while running at lower gain.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E62B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
W78E62B Special Function Registers (SFRs) and Reset Values
F8 F0 E8 E0 D8 D0 C8 C0 B8 +ACC 00000000 +P4 xxxx1111 +PSW 00000000 +T2CON 00000000 XICON 00000000 +IP 00000000 RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 SFRFD 00000000 SFRCN 00000000 CHPCON 0xx00000 D7 CF C7 BF +B 00000000 CHPENR 00000000 FF F7 EF E7 DF
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W78E62B
W78E62B Special Function Registers (SFRs) and Reset Values, continued
B0 A8 A0 98 90 88 80 +P3 00000000 +IE 00000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 SBUF xxxxxxxx P41AL 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 PCON 00110000 8F 87 P2EAL 00000000 P2EAH 00000000 P43AL 00000000 P42AL 00000000 P43AH 00000000 P42AH 00000000 P2ECON 0000xx00 A7 9F 97 B7 AF
Note: 1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers.
P4CONB (C3H)
BIT 7, 6 NAME P43FUN1 P43FUN0 FUNCTION 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 01: Compare the 15 high bits (A15-A1) of address bus with the base address register P43AH, P43AL. 10: Compare the 14 high bits (A15-A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15-A8) of address bus with the base address register P43AH, P43AL. The P4.2 function control bits which are the similar definition as P43FUN1, P43FUN0. The P4.2 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.
5, 4
P43CMP1 P43CMP0
3, 2 1, 0
P42FUN1 P42FUN0 P42CMP1 P42CMP0
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W78E62B
P4CONA (C2H)
BIT 7, 6 5, 4 3, 2 1, 0 NAME P41FUN1 P41FUN0 P41CMP1 P41CMP0 P40FUN1 P40FUN0 P40CMP1 P40CMP0 FUNCTION The P4.1 function control bits which are the similar definition as P43FUN1, P43FUN0. The P4.1 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0. The P4.0 function control bits which are the similar definition as P43FUN1, P43FUN0. The P4.0 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.
Port 4 Base Address Registers
P40AH, P40AL: The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address.
The SFR for Port 4
P4 (D8H) BIT 7 6 5 4 3 2 1 0 NAME P43 P42 P41 P40 FUNCTION Reserve Reserve Reserve Reserve Port 4 Data bit which outputs to pin P4.3 at mode 0. Port 4 Data bit. which outputs to pin P4.2 at mode 0. Port 4 Data bit. which outputs to pin P4.1at mode 0. Port 4 Data bit which outputs to pin P4.0 at mode 0.
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W78E62B
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H- 1237H and positive polarity, and P4.1-P4.3 are used as general I/O ports. MOV P40AH,#12H MOV P40AL,#34H MOV P4CONA,#00001010B MOV P4CONB,#00H MOV P2ECON,#10H MOV CHPENR,#00H ; Define the base I/O address 1234H for P4.0 as an special function ; pin ; Define the P4.0 as a write strobe signal pin and the comparator ; length ;is 14 ; P4.1-P4.3 as general I/O port which are the same as PORT1 ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative. ; Disable CHPCON write attribute.
Then any instruction MOVX @DPTR,A (with DPTR = 1234H-1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4,#XX will output the bit3 to bit1 of data #XX to pin P4.3-P4.1.
PORT 2 OUTPUT DATA BUS INTERNAL DATA BUS PORT 2 74373 WRITE Latch G ADDRESS BUS MUX
EQUAL 16 Bit comparator REGISTER P2EAL P2EAH 74244 Buffer READ G DEMUX
PORT2 INPUT DATA BUS
P2ECON.P2CN0 P2ECON.P2CN1 PORT2 BASIC STRUCTURE
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W78E62B
P2EAH, P2EAL: The Port Enable Address Registers for Port2 as an Input Buffer/Output-Latched Port. The I/O port enable address is need to assign when Port2 is defined as input buffer like a 74244, or a output-latched logic like a 74373. The P2EAH contains the high-order byte of address, the P2EAL contains the low-order byte of address. The following example shows how to program the Port 2 as a output-latched port at address 5678H. MOV P2EAL,#78H MOV P2EAH,#56H MOV P2ECON,#02H MOV DPTR,#5678H MOV A, #55H MOVX @DPTR, A ; The pins P2.7-P2.0 will output and latch the value 55H. ; High-order byte of address to enable Port2 latch function. ; Low-order byte of address to enable Port2 latch function. ; Configure the Port2 as an output-latched port. ; Move data 5678H to DPTR.
When Port2 is configured as 74244 or 74373 function, the instruction " MOV P2,#XX " will write the data #XX to P2 register only but not output to port pins P2.7-P2.0.
Port 2 Expanded Control Register(P2ECON).
P2ECON (AEH) BIT 7 NAME FUNCTION P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1 : P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal. = 0 : P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. P42CSINV The similarity definition as P43SINV. P41CSINV The similarity definition as P43SINV. P40CSINV The similarity definition as P43SINV. Reserve Reserve P2CN1, 00 : Pins P2.7-P2.0 is the standard 8051 Port 2. P2CN0 01 : Pins P2.7-P2.0 is input buffer port which the port enable address depends on the content of P2EAL and P2EAH 10 : Pins P2.7-P2.0 is output-latched port which the port enable address depends on the content of P2EAL and P2EAH. 11 : Undefined.
6 5 4 3 2 1, 0
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W78E62B
P4xCSINV P4 REGISTER P4.x DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE
RD/WR_CS PIN P4.x
ADDRESS BUS EQUAL REGISTER P4xAL P4xAH
P4xFUN0 P4xFUN1
Bit Length Selectable comparator REGISTER P4xCMP0 P4xCMP1
P4.x INPUT DATA BUS
Port 4 Block Diagram
In-System Programming (ISP) Mode
The W78E62B equips one 64K byte of main MTP-ROM bank for application program (called APROM) and one 4K byte of auxiliary MTP-ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E62B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78E62B achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ...etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for wake-up from idle mode. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible that the end-user is able to easily update the system firmware by themselves without opening the chassis.
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W78E62B
SFRAH,SFRAL:
The objective address of on-chip MTP-ROM in the in-system programming mode. SFRFAH contains the high-order byte of address, SFRFAL contains the low-order byte of address.
SFRFD:
The programming data for on-chip MTP-ROM in programming mode.
SFRCN:
The control byte of on-chip MTP-ROM programming mode.
SFRCN (C7)
BIT 7 6 NAME WFWIN Reserve. On-chip MTP-ROM bank select for in-system programming. = 0 : 64K bytes MTP-ROM bank is selected as destination for re-programming. = 1 : 4K bytes MTP-ROM bank is selected as destination for re-programming. 5 4 3, 2, 1, 0 OEN CEN MTP-ROM output enable. MTP-ROM chip enable. FUNCTION
CTRL[3:0] The flash control signals
Mode
Erase 64 KB APROM Program 64 KB APROM Read 64 KB APROM Erase 4 KB LDROM Program 4 KB LDROM Read 4 KB LDROM
WFWIN
0 0 0 1 1 1
CTRL<3:0>
0010 0001 0000 0010 0001 0000
OEN
1 1 0 1 1 0
CEN
0 0 0 0 0 0
SFRAH,SFRAL
X Address in Address in X Address in Address in
SFRFD
X Data in Data out X Data in Data out
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W78E62B
In-System Programming Control Register (CHPCON)
CHPCON (BFH) BIT 7 NAME
SWRESET (F04KMODE)
FUNCTION When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. This action will re-boot the microcontroller and start to normal operation. To read this bit in logic-1 can determine that the F04KBOOT mode is running. Reserve. Reserve. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM must set to 0. must set to 0. The Program Location Select. 0: The Loader Program locates at the 64 KB APROM. 4 KB LDROM is destination for re-programming. 1: The Loader Program locates at the 4 KB memory bank. 64 KB APROM is destination for re-programming.
6 5 4 3 2 1
ENAUXRAM
0 0 FBOOTSL
0
FPROGEN
MTP-ROM Programming Enable. = 1:enable. The microcontroller enter the in-system programming mode after entering the idle mode and wake-up from interrupt. During in-system programming mode, the operation of erase, program and read are acheived when device enters idle mode. = 0 0:disable. The on-chip flash memory is read-only. In-system programmability is disabled.
F04KBOOT Mode (Boot From LDROM )
By default, the W78E62B boots from APROM program after a power on reset. On some occasions, user can force the W78E62B to boot from the LDROM program via following settings. The possible situation that you need to enter F04KBOOT mode is when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this F04KBOOT mode to force the W78E62B jumps to LDROM and excutes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78E62B to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode.
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W78E62B
F04KBOOT MODE P4.3 X L P2.7 L X P2.6 L X Mode FO4KBOOT FO4KBOOT
The Reset Timing For Entering F04KBOOT Mode
P2.7
Hi-Z
P2.6
Hi-Z
RST
30 mS 10 mS
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W78E62B
The Algorithm of In-System Programming
* ***** ** * * * ** * * * * START * ***** * **** **** ****** ** ** * **** ** *** *** * ** * ** * * *
Enter In-System Programming Mode ? (conditions depend on user's application) Yes
No
Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H
Execute the normal application program
Setting Timer (about 1.5us) and enable timer interrupt
END
Start Timer and enter idle Mode. ( CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode)
CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program.
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W78E62B
Part 2: 4KB LDROM
Go Procedure of Updating the 64KB APROM
* ** ***** ***** * *** *** ***** * * *** ** * ** * ** ** * *** ** *** * ***** ***** * * ** *
Is F04KBOOT Mode? (CHPCON.7=1)
Yes End of Programming ?
Yes
No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H
No
Setting Timer and enable Timer interrupt for wake-up . (150us for program operation)
Is currently in the F04KBOOT Mode ?
Yes
No * * *** * ** ******** * * *** * **** * * ***** * *** *** * * * * ** * * * * * * ** * * * * * ** * * * * * * ** * * * * * ** * * * * * * ** * * * * * ** * * *
Setting Timer and enable Timer interrupt for wake-up . (15ms for erasing operation)
Get the parameters of new code (Address and data bytes) through I/O ports, UART or other interfaces.
Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM) * * * * * * * *
Start Timer and enter IDLE Mode. (Erasing...)
* * * *
* * **** * *** * *** ***** ********* * * ** * *** * ** * * ** * * * * ** * * * * * * * * * ** * * * * ** * * * * * * * * * ** * * * * ** * * * * ** * * * * ** * * *
* *** * ***** ******* ***** * * * *** * ** ** ** * * * * * * * * **** ** ********* ** * **** ***** * * * * * * * * *** *
End of erase operation. CPU will be wakened by Timer interrupt.
** *
* * *** *** * ** ** ** * * ***** * *** * **** * * * *** *** *** * * * ** * * * * *
** *
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Publication Release Date: June 1999 Revision A1
W78E62B
Security
During the on-chip MTP-ROM programming mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP-ROM and those operations on it are described below. The W78E62B has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in programming mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The contents of the Company ID and Device ID registers have been set in factory. The Security Register is located at the 0FFFFH of the LDROM space.
D7 D6 D5 D4 D3 D2 D1 D0 11011010 0
B7
Company ID (#DAH) Device ID (#62H) Security Bits
1
1
0
0
0
1
0
4KB MTP ROM Program Memory LDROM
0000h
0FFFh
64KB MTP ROM Program Memory APROM
Reserved
B2 B1 B0
B0 : Lock bit, logic 0 : active B1 : MOVC inhibit, logic 0 : the MOVC instruction in external memory cannot access the code in internal memory. logic 1 : no restriction. B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable B7 : Osillator Control logic 0 : 1/2 gain logic 1 : Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1.
Reserved Reserved
Security Register
FFFFh
Special Setting Registers
Lock bit This bit is used to protect the customer's program code in the W78E62B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.
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W78E62B
Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. Oscillator Control W78E62B allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and C1,C2 may need some adjustment while running at lower gain.
ABSOLUTE MAXIMUM RATINGS
ITEM 1 2 3 4 SYMBOL VDD-VSS VIN TA TST PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature MIN. -0.3 VSS -0.3 0 -55 MAX. +6.0 VDD +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
D.C. ELECTRICAL CHARACTERISTICS
(VDD-VSS = 5V10%, TA = 25 C, Fosc = 20 MHz, unless otherwise specified.)
SYMBOL VDD IDD IIDLE IPWDN IIN1 IIN2
PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST -10 4.5 -50
SPECIFICATION MIN. MAX. 5.5 20 6 50 +10 +300 UNIT V mA mA A A A
TEST CONDITIONS RST = 1, P0 = VDD No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0- 19 -
Publication Release Date: June 1999 Revision A1
W78E62B
D.C. Electrical characteristics, continued
SYMBOL VIL1
PARAMETER Input Low Voltage P0, P1, P2, P3, P4, EA 0
SPECIFICATION MIN. MAX. 0.8 UNIT V
TEST CONDITIONS VDD = 4.5V
VIL2 VIL3 VIH1
Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage P0, P1, P2, P3, P4, EA
0 0 2.4
0.8 0.8 VDD+0.2
V V V
VDD = 4.5V VDD = 4.5V VDD = 5.5V
VIH2 VIH3 VOL1 VOL2
Input High Voltage RST Input High Voltage XTAL1[*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN
[*3]
3.5 3.5 -
VDD+0.2 VDD+0.2 0.45 0.45
V V V V
VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA
Isk1 Isk2
Sink current P1, P3, P4 Sink current P0, P2, ALE, PSEN
4 10
12 20
mA mA
VDD = 4.5V Vin = 0.45V VDD = 4.5V Vin = 0.45V
VOH1 VOH2
Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN
[*3]
2.4 2.4
-
V V A mA
VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A
Isr1 Isr2
Source current P1, P2, P3, P4 Source current P0, P2, ALE, PSEN
-120 -8
-250 -20
VDD = 4.5V Vin = 2.4V VDD = 4.5V Vin = 2.4V
Notes: *1. RST pin is a Schmitt trigger input. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3 , P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V.
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W78E62B
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a * * 20 nS variation. The numbers below represent the performance expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH F OP, TCP TCL
PARAMETER Operating Speed Clock Period Clock High Clock Low
SYMBOL FOP TCP TCH TCL
MIN. 0 25 10 10
TYP. -
MAX. 40 -
UNIT MHz nS nS nS
NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
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Publication Release Date: June 1999 Revision A1
W78E62B
Program Fetch Cycle
PARAMETER Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP- TYP. 2 TCP 3 TCP MAX. 2 TCP 1 TCP 1 TCP UNIT nS nS nS nS nS nS nS nS 4 4 NOTES 4 1, 4 4 2 3
PSEN Low to Data Valid
Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER ALE Low to RD Low RD Low to Data Valid Data Hold from RD High Data Float from RD High RD Pulse Width SYMBOL TDAR TDDA TDDH TDDZ TDRD MIN. 3 TCP- 0 0 6 TCP- TYP. 6 TCP MAX. 3 TCP+ 4 TCP 2 TCP 2 TCP UNIT nS nS nS nS nS 2 NOTES 1, 2 1
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
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W78E62B
Data Write Cycle
ITEM ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. 3 TCP- 1 TCP- 1 TCP- 6 TCP- TYP. 6 TCP MAX. 3 TCP+ UNIT nS nS nS nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. MAX. UNIT nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
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Publication Release Date: June 1999 Revision A1
W78E62B
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA TDAR TDDA
PORT 0 T DDH, TDDZ RD TDRD
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
TDWD
TDAW
TDWR
- 24 -
W78E62B
Port Access Cycle
S5 XTAL1 S6 S1
ALE TPDS PORT TPDH TPDA DATA OUT
INPUT SAMPLE
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Publication Release Date: June 1999 Revision A1
W78E62B
TYPICAL APPLICATION CIRCUIT
Expanded External Program Memory and Crystal
V DD V DD 35 21 10 u
CRYSTAL
EA XTAL1
R 22 XTAL2 10 RST
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
43 AD0 42 AD1 41 AD2 40 AD3 39 AD4 38 AD5 37 AD6 36 AD7 24 25 26 27 28 29 30 31 19 18 32 33 13 11 A8 A9 A10 A11 A12 A13 A14 A15
AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7
14 15 16 17 2 3 4 5 6 7 8 9
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78E62BP
OC 11 G 74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND 20 CE 22 OE 2764
Figure A
CRYSTAL 6 MHz 16 MHz 24 MHz 32 MHz 40 MHz
C1 47P 30P 15P 10P 5P
C2 47P 30P 10P 10P 5P
R 6.8K 4.7K
Above table shows the reference values for crystal applications.
Note1: C1, C2, R components refer to Figure A Note2: Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
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W78E62B
Expanded External Data Memory and Oscillator
VDD VDD 35 21 10 u
OSCILLATOR
EA XTAL1 XTAL2
20 8.2 K
10 RST 14 15 16 17 2 3 4 5 6 7 8 9 INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78E62BP
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 18 32 33 13 11
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
OC 11 G 74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 GND 20 22 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256
D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure B
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Publication Release Date: June 1999 Revision A1
W78E62B
PACKAGE DIMENSIONS
44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Dimension in mm
Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71
Min. Nom. Max.
4.699
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050 0.590 0.590 0.680 0.680 0.090
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27 14.99 14.99 17.27 17.27 2.296
BSC 16.00 16.00 17.78 17.78 2.794 0.10
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
e
Seating Plane GD
b b1
A1 y
48-pin LQFP
HD D
36 25
Symbol
Dimension in mm Min. Nom.
--0.05 1.35 0.17 0.09 ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 0.45 0.60 1.00 --0 0.08 3.5 --7 0.75
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
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W78E62B
Application Note: In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78E62B MTP-ROM microcontroller. In this example, microcontroller will boot from 64KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64KB APROM. While entering in-system programming mode, microcontroller excutes the loader program in 4KB LDROM bank. The loader program erases the 64KB APROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 64KB APROM. EXAMPLE 1: ;******************************************************************************************************************* ;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating thecontents of APROM code else excutes the current ROM code. ;* XTAL = 40 MHz ;*******************************************************************************************************************
.chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU BFH F6H C4H C5H C6H C7H
ORG 0H LJMP 100H ;JUMP TO MAIN PROGRAM ;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG 00BH CLR TR0 ;TR0 = 0,STOP TIMER0 MOV TL0,R6 MOV TH0,R7 RETI ;************************************************************************ ;* 64K APROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A,P1 ANL A,#01H CJNE A,#01H,PROGRAM_64K JMP NORMAL_MODE ;SCAN P1.0 ;IF P1.0=0, ENTER IN-SYSTEM PROGRAMMING MODE
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Publication Release Date: June 1999 Revision A1
W78E62B
PROGRAM_64K: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H MOV TCON,#00H MOV IP,#00H MOV IE,#82H MOV R6,#FEH MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV TMOD,#01H MOV TCON,#10H MOV PCON,#01H
;CHPENR = 87H, CHPCON REGISTER WRTE ENABLE ;CHPENR = 59H, CHPCON REGISTER WRITE ENABLE ;CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE ;TR = 0 TIMER0 STOP ;IP = 00H ;TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ;TL0 = FEH ;TH0 = FFH
;TMOD = 01H,SET TIMER0 A 16-BIT TIMER ;TCON = 10H,TR0 = 1,GO ;ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ;PROGRAMMABILITY ;******************************************************************************** ;* Normal mode 64KB APROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . ;User's application program . . . .
EXAMPLE 2:
;***************************************************************************************************************************** ;* Example of 4KB LDROM program: This lorder program will erase the 64KB APROM first, then reads the new ;* code from external SRAM and program them into 64KB APROM bank. XTAL = 40 MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H BFH F6H C4H C5H C6H C7H
;JUMP TO MAIN PROGRAM
;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ;TR0 = 0,STOP TIMER0 MOV TL0,R6 MOV TH0,R7 RETI
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W78E62B
;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_4K: MOV CHPENR,#87H MOV CHPENR,#59H MOV A,CHPCON ANL A,#80H CJNE A,#80H,UPDATE_64K MOV CHPCON,#03H MOV CHPENR,#00H MOV TCON,#00H MOV TMOD,#01H MOV IP,#00H MOV IE,#82H MOV R6,#FEH MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV TCON,#10H MOV PCON,#01H ;CHPENR = 87H, CHPCON WRITE ENABLE. ;CHPENR = 59H, CHPCON WRITE ENABLE.
;CHECK F04KBOOT MODE ? ;CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. ;DISABLE CHPCON WRITE ATTRIBUTE ;TCON = 00H ,TR = 0 TIMER0 STOP ;TMOD = 01H ,SET TIMER0 A 16BIT TIMER ;IP = 00H ;IE = 82H, TIMER0 INTERRUPT ENABLED
;TCON = 10H,TR0 = 1,GO ;ENTER IDLE MODE
UPDATE_64K: MOV CHPENR,#00H MOV TCON,#00H MOV IP,#00H MOV IE,#82H MOV TMOD,#01H MOV R6,#3CH ;DISABLE CHPCON WRITE-ATTRIBUTE ;TCON = 00H ,TR = 0 TIM0 STOP ;IP = 00H ;IE = 82H,TIMER0 INTERRUPT ENABLED ;TMOD = 01H ,MODE1 ;SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15ms. DEPENDING ;ON USER'S SYSTEM CLOCK RATE. MOV R7,#B0H MOV TL0,R6 MOV TH0,R7 ERASE_P_4K: MOV SFRCN,#22H MOV TCON,#10H MOV PCON,#01H
;SFRCN(C7H) = 22H ERASE 64K ;TCON = 10H,TR0 = 1,GO ;ENTER IDLE MODE( FOR ERASE OPERATION)
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Publication Release Date: June 1999 Revision A1
W78E62B
;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN,#0H MOV SFRAH,#0H MOV SFRAL,#0H MOV R6,#FBH MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 BLANK_CHECK_LOOP: SETB TR0 MOV PCON,#01H MOV A,SFRFD ;ENABLE TIMER 0 ;ENTER IDLE MODE ;READ ONE BYTE ;READ 64KB APROM MODE ;START ADDRESS = 0H ;SET TIMER FOR READ OPERATION, ABOUT 1.5us.
CJNE A,#FFH,BLANK_CHECK_ERROR INC SFRAL ;NEXT ADDRESS MOV A,SFRAL JNZ BLANK_CHECK_LOOP INC SFRAH MOV A,SFRAH CJNE A,#0H,BLANK_CHECK_LOOP ;END ADDRESS=FFFFH JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1,#F0H MOV P3,#F0H JMP $ ;******************************************************************************* ;* RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV DPTR,#0H MOV R2,#00H MOV R1,#00H MOV DPTR,#0H MOV SFRAH,R1 MOV SFRCN,#21H MOV R6,#0CH MOV R7,#FEH MOV TL0,R6 MOV TH0,R7 ;THE ADDRESS OF NEW ROM CODE ;TARGET LOW BYTE ADDRESS ;TARGET HIGH BYTE ADDRESS ;EXTERNAL SRAM BUFFER ADDRESS ;SFRAH, TARGET HIGH ADDRESS ;SFRCN(C7H) = 21 (PROGRAM 64K) ;SET TIMER FOR PROGRAMMING, ABOUT 150us.
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W78E62B
PROG_D_64K: MOV SFRAL,R2 ;SFRAL(C4H)= LOW BYTE ADDRESS MOVX A,@DPTR ;READ DATA FROM EXTERNAL SRAM BUFFER MOV SFRFD,A ;SFRFD(C6H) = DATA IN MOV TCON,#10H ;TCON = 10H,TR0 = 1,GO MOV PCON,#01H ;ENTER IDLE MODE( PRORGAMMING) INC DPTR INC R2 CJNE R2,#0H,PROG_D_64K INC R1 MOV SFRAH,R1 CJNE R1,#0H,PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R4,#03H ;ERROR COUNTER MOV R6,#FBH ;SET TIMER FOR READ VERIFY, ABOUT 1.5us. MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV DPTR,#0H ;The start address of sample code MOV R2,#0H ;Target low byte address MOV R1,#0H ;Target high byte address MOV SFRAH,R1 ;SFRAH, Target high address MOV SFRCN,#00H ;SFRCN = 00 (Read ROM CODE) READ_VERIFY_64K: MOV SFRAL,R2 ;SFRAL(C4H) = LOW ADDRESS MOV TCON,#10H ;TCON = 10H,TR0 = 1,GO MOV PCON,#01H INC R2 MOVX A,@DPTR INC DPTR CJNE A,SFRFD,ERROR_64K CJNE R2,#0H,READ_VERIFY_64K INC R1 MOV SFRAH,R1 CJNE R1,#0H,READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR,#87H ;CHPENR = 87H MOV CHPENR,#59H ;CHPENR = 59H MOV CHPCON,#83H ;CHPCON = 83H, SOFTWARE RESET.
ERROR_64K: DJNZ R4,UPDATE_64K ;IF ERROR OCCURS, REPEAT 3 TIMES. . ;IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. . . .
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Publication Release Date: June 1999 Revision A1
W78E62B
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Price & Availability of W78E62B

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